Semiconductor memory devices such as a dynamic random access memory, include a memory cell array and a bit line pair for transferring data.
Writing data to a specific memory cell in a memory cell array or reading the data from the specific memory cell is performed by transmitting the data in the memory cell to a bit line by charge sharing. The data is then sensed using the difference in potential between the bit line and a bit line bar.
FIG. 1 is a circuit diagram showing a prior art bit line control circuit. The conventional bit line controlling circuit includes data lines 110 and 120, an equalizing and precharging portion 130, a memory cell array 140 and a sense and amplification portion 150.
The memory cell array 140 includes a plurality of memory cells each connected to the data lines 110 and 120. Each memory cell has a cell transistor and a cell capacitor. The memory cells are accessed by corresponding addresses and store data in the form of charge in a corresponding cell capacitor. A cell transistor is gated by a word line and transmits charge stored in a cell capacitor to a corresponding data line.
The data lines 110 and 120 act as a bit line (BL) and a bit line bar (/BL) with respect to corresponding memory cells. That is, if a memory cell selected for reading information is connected to the data line 110, the data line 110 becomes the bit line (BL) and the data line 120 becomes the bit line bar (/BL). On the other hand, if a memory cell selected for reading information is connected to the data line 120, the data line 120 becomes the bit line (BL) and the data line 110 becomes the bit line bar (/BL).
The equalizing and precharging portion 130 is connected between the data lines 110 and 120, controlled by an equalization control signal PEQ, and precharges the data lines 110 and 120 to equalization voltage VBL for a period of precharging. When the data line acting as the bit line BL shares charges, the equalizing and precharging portion 130 floats the data lines 110 and 120.
The sense and amplification portion 150 is controlled by a sensing control signal PIS, and senses and amplifies the difference in a voltage level between data lines 110 and 120.
Writing data into the memory cell array is performed by searching for the location of a desired memory cell. The location is determined by a combination of addresses applied from an external source. The data input in association with an address is converted into a charge to be stored in a cell capacitor in a designated memory cell. Reading the data is performed by converting the charge stored in the memory cell to a voltage, amplifying the converted voltage, and transmitting the amplified voltage to the outside.
Procedures of reading data stored in a desired memory cell will be described as follows. The data lines 110 and 120 are precharged to equalization voltage VBL by the equalizing and precharging portion 130 for a period of precharging.
When the word line of a cell transistor in a corresponding memory cell is driven by a row address strobe signal RASB, the equalization controlling signal PEQ disables the equalizing and precharging portion 130, floating the precharged data lines 110 and 120.
According to where the desired memory cell is connected, one of the data lines 110 and 120 acts as the bit line. The charge stored in the memory cell is shared until the level of a storage node voltage Vs in the memory cell equals the voltage of the data line acting as the bit line. When the charge sharing operation is completed, the sense and amplification portion 150 senses the difference in potential between the data lines 110 and 120, amplifies the difference and then outputs the result under the control of a sensing control signal PIS.
FIG. 2 is a timing chart of each signal on the bit line control circuit shown in FIG. 1.
An equalizing signal PEQ is active during precharging. After precharging, the equalizing signal PEQ disables the equalizing and precharging portion 130 to float the data lines 110 and 120 precharged to the equalization voltage VBL.
A driving signal PIX is activated driving a word line corresponding to the row address strobe signal RASB. A data line connected to a corresponding memory cell (which is accessed by a driven word line) among the data lines 110 and 120 begins to share charge with the corresponding memory cell (refer to t1 of FIG. 2).
After a predetermined period of time, that is, after the potential of the data line and that of the memory cell are equalized by charge sharing (refer to t2 of FIG. 2), the sensing control signal PIS is activated enabling the sense and amplification portion 150.
In conventional bit line controlling circuits, while the data line acting as the bit line shares charge with a memory cell, the data line acting as the bit line bar floats while being precharged to the equalization voltage VBL. Therefore, during charge sharing from a period of time between t1 and t2 of FIG. 2, a coupling effect occurs between the data line acting as the bit line and that acting as the bit line bar. That is, the voltage level of the data line acting as the bit line varies due to charge sharing with a corresponding memory cell. The voltage level of the data line acting as the bit line bar is also changed. Consequently, the difference in voltage levels between the data lines after charge sharing becomes smaller than a predetermined value which can be accurately sensed by the sense and amplification portion.
Furthermore, as integration of memory cells increase, the time interval between the data lines acting as the bit line and the bit line bar becomes smaller. Embedded memory devices include an Application Specific Integrated Circuit (ASIC) field and a DRAM circuit manufactured on a signal chip. Accordingly, material layers of the data lines acting as the bit line and the bit line bar are replaced by metal layers instead of poly layers employed in the prior art. Thus, the vertical heights of the data lines acting as the bit line and the bit line bar increases increasing coupling capacitance. As a result, coupling effects of the data lines becomes worse, adversely effecting the sensing operation performed by the sense and amplification portion.
FIG. 3 shows the coupling effect occurring between the bit line and the bit line bar, in the conventional bit line controlling circuit of FIG. 1. Here, a vertical axis denotes the level of voltage and a horizontal axis denotes the time. Reference numerals 160 and 170 denote the potential values of the bit line and the bit line bar, respectively. Reference numeral t1 is the time when the charge sharing starts, and reference numeral t2 is the time when the sensing and amplifying operation starts being performed by the sense and amplification portion 150.
Referring to FIG. 3, during precharging, the bit line and the bit line bar are precharged to the equalization voltage VBL before charge sharing. During charge sharing (between t1 and t2), the potential of the bit line changes to VH due to the charge sharing of the bit line with a corresponding memory cell. The potential of the bit line bar is also changed into VHB due to the coupling effect with the bit line. Accordingly, after the time for charge sharing ends, the difference (VH-VHB) in potential between the bit line and the bit line bar becomes smaller than a predetermined value which can be effectively sensed by the sense and amplification portion 150. Thus, accurate data reading is difficult.